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19251
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Untitled by @neilsarkar | Stardance
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neilsarkar
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0
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0.0
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0
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[]
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[]
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Title: Untitled by @neilsarkar | Stardance
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1793469334.578863
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1794074134.578863
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19252
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My very own WebOS by @Chip | Stardance
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Chip
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0
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0.0
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0
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[]
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[]
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Title: My very own WebOS by @Chip | Stardance
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1794030474.9505446
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1794635274.9505446
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19253
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My very own WebOS by @JasonW | Stardance
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JasonW
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1
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5.0
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0
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[{"ship_num": 1, "ts": "2026-0 [{"ship_num": 1, "ts": "2026-06-20T14:33:04Z", "hours": 5.0, "multiplier": null, "payout": 0, "blessing": "neutral", "text": "I made a website that resembles my custom operating system. It features different windows as applications. The features for the windows include being draggable, and being reopenable. I also added a small timer app that can be used for studying and other stuff!", "repo": "https://github.com/jsn-w/wei-OS", "demo": "https://jsn-w.github.io/wei-OS/"}]...
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[{"post_id": 12541, "ts": "202 [{"post_id": 12541, "ts": "2026-06-20T14:19:17Z", "hours": 0.3631, "text": "added logic for the timer. you are able to start, pause, reset and also add/subtract time from it"}, {"post_id": 10173, "ts": "2026-06-16T19:44:42Z", "hours": 1.2439, "text": "i added logic for multiple desktop icons that open and close when each of them is pressed. i also added the ui for the timer, i still need to work on that logic. i also added some hover effects on the buttons which turned out really nicely!"}, {"post_id": 9671, "ts": "2026-06-16T02:34:45Z", "hours": 0.3881, "text": "I added a button on the screen to open the about me tab when the window is closed. I also modified the javascript so that when the user is dragging the window, it stays within the window."}, {"post_id": 9648, "ts": "2026-06-16T01:46:02Z", "hours": 1.1994, "text": "I made the window draggable and added some nuances (highlight text, etc). It took me a while to figure out the layout of the divs, but it turned out really nice. I would also like to add some transition time to smooth things out."}, {"post_id": 9558, "ts": "2026-06-15T22:41:20Z", "hours": 1.605, "text": "I implemented a background, taskbar, and a little about-me page."}]...
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Title: My very own WebOS by @JasonW | Stardance
D Title: My very own WebOS by @JasonW | Stardance
Devlogs:
I implemented a background, taskbar, and a little about-me page.
I made the window draggable and added some nuances (highlight text, etc). It took me a while to figure out the layout of the divs, but it turned out really nice. I would also like to add some transition time to smooth things out.
I added a button on the screen to open the about me tab when the window is closed. I also modified the javascript so that when the user is dragging the window, it stays within the window.
i added logic for multiple desktop icons that open and close when each of them is pressed. i also added the ui for the timer, i still need to work on that logic. i also added some hover effects on the buttons which turned out really nicely!
added logic for the timer. you are able to start, pause, reset and also add/subtract time from it
Ships:
I made a website that resembles my custom operating system. It features different windows as applications. The features for the windows include being draggable, and being reopenable. I also added a small timer app that can be used for studying and other stuff!...
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1793886994.2279086
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1793973394.2279086
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19254
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My very own WebOS by @sai_medarametla765 | Stardan My very own WebOS by @sai_medarametla765 | Stardance...
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sai_medarametla765
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0
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0.0
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0
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[]
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Title: My very own WebOS by @sai_medarametla765 | Title: My very own WebOS by @sai_medarametla765 | Stardance...
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1793958658.6972413
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1794563458.6972413
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19255
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Moonlander by @FoolishGenius | Stardance
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FoolishGenius
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0
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0.0
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0
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[]
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[]
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Title: Moonlander by @FoolishGenius | Stardance
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1793843540.704106
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1794448340.704106
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19256
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My very own WebOS by @nity | Stardance
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nity
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0
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0.0
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0
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[]
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[]
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Title: My very own WebOS by @nity | Stardance
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1793933787.0380626
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1794538587.0380626
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19257
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Untitled by @alvindandme | Stardance
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alvindandme
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0
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0.0
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0
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[]
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[]
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Title: Untitled by @alvindandme | Stardance
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1793832576.8254333
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1794437376.8254333
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19258
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basketball counter by @ | Stardance
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0
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0.0
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0
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[]
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[]
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Title: basketball counter by @ | Stardance
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1793425689.2919238
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1794030489.2919238
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19259
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Reo's Solar Neighborhood by @Reo | Stardance
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Reo
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0
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0.0
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0
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[]
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[]
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Title: Reo's Solar Neighborhood by @Reo | Star Title: Reo's Solar Neighborhood by @Reo | Stardance...
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1793371902.1352
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1793976702.1352
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19260
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Atlas Astro by @Astro-Vasudha | Stardance
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Astro-Vasudha
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0
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0.0
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0
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[]
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[]
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Title: Atlas Astro by @Astro-Vasudha | Stardance
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1793998145.226498
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1794602945.226498
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19261
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Frictionless by @reynaldo000786 | Stardance
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reynaldo000786
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0
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0.0
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0
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[]
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[]
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Title: Frictionless by @reynaldo000786 | Stardance
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1793451026.4979577
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1794055826.4979577
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19262
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Frictionless by @Parker | Stardance
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Parker
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0
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0.0
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0
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[]
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[]
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Title: Frictionless by @Parker | Stardance
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1793321667.712719
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1793926467.712719
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19263
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The Gamer test by @KHUSHAL | Stardance
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KHUSHAL
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0
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0.0
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0
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[]
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[]
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Title: The Gamer test by @KHUSHAL | Stardance
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1793519706.3073823
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1794124506.3073823
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19264
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meowOS by @arman | Stardance
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arman
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1
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9.0
|
164
|
[{"ship_num": 1, "ts": "2026-0 [{"ship_num": 1, "ts": "2026-06-24T12:38:21Z", "hours": 9.0, "multiplier": 17.32, "payout": 164, "blessing": "neutral", "text": "What did I make? A browser based desktop OS. It has a boot screen, a window manager, a taskbar, desktop widgets, and seven apps and its all cat themed. You can open and drag windows around, change your wallpaper, use a terminal, write notes, check the time. It actually feels like an OS, which was the whole point. Live at https://meowos-web.vercel.app What was challenging? SSR kept biting me. Next.js renders on the server first, so anything touching localStorage or window would crash on Vercel even when it worked fine locally. Took a while to track down every spot that needed a guard. The window maximize animation also gave me grief windows would snap and drag at the same time in this weird magnet effect. Fixed it by separating animation state from logical state so the transition only fires during the toggle, not while dragging. I also tried adding route transition fades between boot, shutdown, and desktop. Spent a few hours on it, kept breaking things, eventually just cut it. What am I proud of? The boot screen. Kernel text prints line by line, fades into a paw icon, then routes to the desktop. It’s a small thing but it makes the whole OS feel real. How to test it? Go to https://meowos-web.vercel.app you’ll land on the shutdown screen, click to boot.", "repo": "https://github.com/armansinghh/WebOS", "demo": "https://meowos-web.vercel.app/"}]...
|
[{"post_id": 15021, "ts": "202 [{"post_id": 15021, "ts": "2026-06-24T12:26:06Z", "hours": 3.1114, "text": "well its done guys what i built? i actually had no idea what to start with, i saw a webOS listed, thought it was pretty cool… i love cats, so why not build a cat-styled OS? u guys can check it out here: https://meowos-web.vercel.app/ whats next? just check it out guys (pls 🙏) note i wrote a highly technical long dev log but it all vanished when i closed the tab accidently, i dont have energy left to write all over again 😔😔 also follow me on github https://github.com/armansinghh thanks y’all"}, {"post_id": 14184, "ts": "2026-06-23T05:35:23Z", "hours": 5.0883, "text": "Spent a lot of time this session just making things feel right 😮💨 Added boot screen and the best part… Rebuilt most of the apps from scratch basically. PawWatch now has an actual analog clock face with cat ears on top and a digital readout next to it. MeowPad got autosave, word count and char limit. PawShell now remembers your command history and arrow keys work just like a real terminal. The settings app (PawNel) got a full sidebar layout, a live desktop preview when picking wallpapers, and an About page showing the stack. Also added two new apps: File Cat-alog is a file explorer with a fake filesystem you can navigate. Also added PrrSurf, it is a browser with a cat themed homepage with shortcuts to Wikipedia, AccuWeather, and Excalidraw. Taskbar got cleaned up too, the paw menu and control center both feel much more polished now. Honestly meowOS is starting to look like something I’d actually want to use. Next up is some final polish and getting it ready to ship 😝"}, {"post_id": 11296, "ts": "2026-06-18T14:09:31Z", "hours": 1.2869, "text": "Built the core of meowOS today!!! A fully working window manager in the browser. Windows are draggable, resizable, and stack correctly when focused. 4 apps so far: Clock - live time and date Text Editor - write and save notes, persists with localStorage Terminal - commands like help, meow, echo, date Settings - pick from 4 cat wallpapers, choice saves across sessions Stack: Next.js, Tailwind, Zustand, react-rnd, react-icons. Next up: File Explorer and Browser app."}]...
|
Title: meowOS by @arman | Stardance
Devlogs:
Buil Title: meowOS by @arman | Stardance
Devlogs:
Built the core of meowOS today!!! A fully working window manager in the browser. Windows are draggable, resizable, and stack correctly when focused. 4 apps so far: Clock - live time and date Text Editor - write and save notes, persists with localStorage Terminal - commands like help, meow, echo, date Settings - pick from 4 cat wallpapers, choice saves across sessions Stack: Next.js, Tailwind, Zustand, react-rnd, react-icons. Next up: File Explorer and Browser app.
Spent a lot of time this session just making things feel right 😮💨 Added boot screen and the best part… Rebuilt most of the apps from scratch basically. PawWatch now has an actual analog clock face with cat ears on top and a digital readout next to it. MeowPad got autosave, word count and char limit. PawShell now remembers your command history and arrow keys work just like a real terminal. The settings app (PawNel) got a full sidebar layout, a live desktop preview when picking wallpapers, and an About page showing the stack. Also added two new apps: File Cat-alog is a file explorer with a fake filesystem you can navigate. Also added PrrSurf, it is a browser with a cat themed homepage with shortcuts to Wikipedia, AccuWeather, and Excalidraw. Taskbar got cleaned up too, the paw menu and control center both feel much more polished now. Honestly meowOS is starting to look like something I’d actually want to use. Next up is some final polish and getting it ready to ship 😝
well its done guys what i built? i actually had no idea what to start with, i saw a webOS listed, thought it was pretty cool… i love cats, so why not build a cat-styled OS? u guys can check it out here: https://meowos-web.vercel.app/ whats next? just check it out guys (pls 🙏) note i wrote a highly technical long dev log but it all vanished when i closed the tab accidently, i dont have energy left to write all over again 😔😔 also follow me on github https://github.com/armansinghh thanks y’all
Ships:
What did I make? A browser based desktop OS. It has a boot screen, a window manager, a taskbar, desktop widgets, and seven apps and its all cat themed. You can open and drag windows around, change your wallpaper, use a terminal, write notes, check the time. It actually feels like an OS, which was the whole point. Live at https://meowos-web.vercel.app What was challenging? SSR kept biting me. Next.js renders on the server first, so anything touching localStorage or window would crash on Vercel even when it worked fine locally. Took a while to track down every spot that needed a guard. The window maximize animation also gave me grief windows would snap and drag at the same time in this weird magnet effect. Fixed it by separating animation state from logical state so the transition only fires during the toggle, not while dragging. I also tried adding route transition fades between boot, shutdown, and desktop. Spent a few hours on it, kept breaking things, eventually just cut it. What am I proud of? The boot screen. Kernel text prints line by line, fades into a paw icon, then routes to the desktop. It’s a small thing but it makes the whole OS feel real. How to test it? Go to https://meowos-web.vercel.app you’ll land on the shutdown screen, click to boot....
|
1794044929.3070924
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1794131329.3070924
|
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19265
|
NFC Monsters by @radsi | Stardance
|
radsi
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1
|
51.0
|
108
|
[{"ship_num": 1, "ts": "2026-0 [{"ship_num": 1, "ts": "2026-07-13T16:26:11Z", "hours": 51.0, "multiplier": 2.75, "payout": 108, "blessing": "neutral", "text": "This is a mobile game that uses NFC technology to cast spells and execute actions… This is a very WIP project, I can’t event test it on my own phone so I uploaded a showcase video in case someone is interested!", "repo": "https://github.com/radsi/nfc-monsters", "demo": "https://www.youtube.com/watch?v=Tx2pvqhJloY"}]...
|
[{"post_id": 27756, "ts": "202 [{"post_id": 27756, "ts": "2026-07-13T16:22:16Z", "hours": 2.0864, "text": "first alpha release"}, {"post_id": 26628, "ts": "2026-07-11T15:39:57Z", "hours": 5.0958, "text": "New items, enemies, and random events, support for custom music on different map nodes, button to return to the main menu during a run and multiple fixes."}, {"post_id": 24094, "ts": "2026-07-07T13:17:05Z", "hours": 5.1831, "text": "Added a new Layer 3 boss, new events, event-exclusive items and spell unlocks, plus an editor export/import addon. Fixed multiple gameplay and visual bugs, improved random events, and reduced starting HP to 50."}, {"post_id": 20722, "ts": "2026-07-02T12:09:22Z", "hours": 4.9686, "text": "Improved enemy SFX, reworked the armor system into a separate bar, added enemy attack damage indicators, fixed the Spell Summon index bug, improved enemy buffs, and added new events."}, {"post_id": 17744, "ts": "2026-06-28T17:40:48Z", "hours": 4.4111, "text": "Added seed-based generation, new events and items, improved combat feedback, more sound effects, and fixed multiple bugs."}, {"post_id": 15194, "ts": "2026-06-24T18:12:45Z", "hours": 5.4392, "text": "Added unlock notifications, new random events and boss, improved combat feedback, audio, balancing, and added new enemies, items, and spells."}, {"post_id": 12585, "ts": "2026-06-20T15:32:36Z", "hours": 4.0233, "text": "Added new audio, fixed key gameplay bugs, improved UI (tooltips, inventory scroll, gallery), and expanded content with new items, enemies, bosses, and effects."}, {"post_id": 9944, "ts": "2026-06-16T13:58:01Z", "hours": 19.4583, "text": "Slay the Spire inspired game that uses Android NFC to cast spells and perform actions. Right now im working on the base game before starting to add events, items and so"}]...
|
Title: NFC Monsters by @radsi | Stardance
Devlogs Title: NFC Monsters by @radsi | Stardance
Devlogs:
Slay the Spire inspired game that uses Android NFC to cast spells and perform actions. Right now im working on the base game before starting to add events, items and so
Added new audio, fixed key gameplay bugs, improved UI (tooltips, inventory scroll, gallery), and expanded content with new items, enemies, bosses, and effects.
Added unlock notifications, new random events and boss, improved combat feedback, audio, balancing, and added new enemies, items, and spells.
Added seed-based generation, new events and items, improved combat feedback, more sound effects, and fixed multiple bugs.
Improved enemy SFX, reworked the armor system into a separate bar, added enemy attack damage indicators, fixed the Spell Summon index bug, improved enemy buffs, and added new events.
Added a new Layer 3 boss, new events, event-exclusive items and spell unlocks, plus an editor export/import addon. Fixed multiple gameplay and visual bugs, improved random events, and reduced starting HP to 50.
New items, enemies, and random events, support for custom music on different map nodes, button to return to the main menu during a run and multiple fixes.
first alpha release
Ships:
This is a mobile game that uses NFC technology to cast spells and execute actions… This is a very WIP project, I can’t event test it on my own phone so I uploaded a showcase video in case someone is interested!...
|
1793883021.0625527
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1793969421.0625527
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19266
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My first slack bot! by @Aayanhakeem | Stardance
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Aayanhakeem
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0
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0.0
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0
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[]
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[]
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Title: My first slack bot! by @Aayanhakeem | Stard Title: My first slack bot! by @Aayanhakeem | Stardance...
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1794012458.4608033
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1794617258.4608033
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19267
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Design for Atmospheric Shuttle!! by @grippy | Star Design for Atmospheric Shuttle!! by @grippy | Stardance...
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grippy
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0
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0.0
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0
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[]
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[]
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Title: Design for Atmospheric Shuttle!! by @grippy Title: Design for Atmospheric Shuttle!! by @grippy | Stardance...
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1793987284.630166
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1794592084.630166
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19268
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My awesome macropad! by @Rene | Stardance
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Rene
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0
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0.0
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0
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[]
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[]
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Title: My awesome macropad! by @Rene | Stardance
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1793530070.140936
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1794134870.140936
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19269
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DELETED by @Teedious | Stardance
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Teedious
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0
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0.0
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0
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[]
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[]
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Title: DELETED by @Teedious | Stardance
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1794012920.3557115
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1794617720.3557115
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19270
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Frictionless by @Nidhi | Stardance
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Nidhi
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0
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0.0
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0
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[]
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[]
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Title: Frictionless by @Nidhi | Stardance
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1793969601.637263
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1794574401.637263
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19271
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Helios One by @Luka | Stardance
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Luka
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0
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118.35
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0
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[]
|
[{"post_id": 80424, "ts": "202 [{"post_id": 80424, "ts": "2026-10-17T16:26:20Z", "hours": 0.35, "text": "I totally forgot to add Testpoints haha , now there are some on the PWR rails !"}, {"post_id": 79701, "ts": "2026-10-15T03:38:25Z", "hours": 5.2808, "text": "My Last designing Devlog , its been a reallyyyyy long part of the project RadiaX but the FPGA SOM , aswell as the rockchip sbc are finished ! (wich is more of an placeholder rg , because the funding does not make it possible… ) I am happy to ship it NOW !"}, {"post_id": 79604, "ts": "2026-10-14T17:53:16Z", "hours": 7.1186, "text": "Long time no devlog but its just power routing and some tricky layout changes . The only sad part to switch from the kintex7 325T to a smaller variant , same for the ram …. funding 600$ cap :,)"}, {"post_id": 77567, "ts": "2026-10-07T14:35:06Z", "hours": 1.6172, "text": "The SOM was wayyy to expensive for the 600 dollar funding limit … so i had to choose an smaller LUTS fpga model and for it change the recommendet decoupling caps amount . Afterwards I changed some parts for cost saving and played around with coupons till it fit the 600 dollar funding limit … .. ."}, {"post_id": 74653, "ts": "2026-09-27T21:22:01Z", "hours": 9.6522, "text": "SO the devlog may seem long… but i lost 2 hours of footage while routing so yeah .. i routed the ddr3 , that includes the diff pairs , length matching and impedance constrains , etc … bla bla bla tech stuff , this took longer and was harder than the double stack (2 ics in one) lpddr4 on the rockchip board , idk why , propably placement and fpgas being tricky in general !"}, {"post_id": 72412, "ts": "2026-09-22T21:19:04Z", "hours": 1.2108, "text": "So marco made the Kintex Fpga a 3d model , there werent any good ones out there … Its the big metal thingy you can see in the middle of the Pcb . He send me the wrong footprint to installed freecad and resized it (I like fusion360 but i dont have it installed on my new laptop..) , Also I rendered the Pcb in blender ! I know the routing isnt finished but i really dont have the energie and time for it today !"}, {"post_id": 71836, "ts": "2026-09-21T16:57:50Z", "hours": 1.65, "text": "I finished the Layout of the FPGA SOM , the filter caps have a really high footprint so that was tricky and the vtt resistors for the ddr3 , its a asingle ddr3 ic so that was weird …"}, {"post_id": 71376, "ts": "2026-09-20T18:29:22Z", "hours": 3.4336, "text": "The fpga SOM is now almost done , this was a faster pcb than i expected , i know it may look messy and crowdet but the pwr stuff is actually layouted in the best possible way(atleast i hope so) and some other things , now only some schematic finishing and checking is needet , then I can route and finish it !"}, {"post_id": 70898, "ts": "2026-09-19T23:55:28Z", "hours": 1.2167, "text": "THXXXX for the SUPER STAR !!!!! I finished the PWR filtering , i had to add some filter caps on the DDR3 . Then i used the LiteX Repo to see if i should add an EMMC , i decidet against it because of cost (already a problem…) and space constrains . But still i had to redo the Prog. section (mostly bank0 on the Kintex7) again because i accedently deleted it many journals ago when i sepperated the rockchip and kintex ! I went with a SPI flash (quad spi) … then I connected some mandatory config and other circuitry , this was mostly straightforward with the ref. designs and the ABSOLUTELY many documents on the AMD Technical Information Portal"}, {"post_id": 70768, "ts": "2026-09-19T18:40:42Z", "hours": 2.7503, "text": "The fpga SOM , PWR system is now finished . I already had the old power system but now its an smaller fpga package and power requirements , so i cleaned up suitable parts , let ai compare some dc/dc board mounts to safe space , designed some power sections and conmbined them all , etc…"}, {"post_id": 70622, "ts": "2026-09-19T14:02:18Z", "hours": 1.5503, "text": "I used the Mig Interface pin xdc file i created to connect the ddr3 to the fpga banks and then made the power interface for it !"}, {"post_id": 70219, "ts": "2026-09-18T18:50:14Z", "hours": 0.8, "text": "I updates some parts , mostly cap placement because it was to crowdet and i made an export of the layers … https://github.com/Luka-io/RadiaX/blob/main/electronics/layers.pdf"}, {"post_id": 70195, "ts": "2026-09-18T17:55:16Z", "hours": 4.6994, "text": "After doing the rockchip sbc , i started with the fpga som , i will redo the power parts as i switched to a fpga (same model) with less pins , and a small package … i laso installed vivado wich totally hanged up my pc so i had to pause work , i needet to do it to get the pinout for the ddr3 to fpga (MIG = memory interface generator wizard) . The layout on the pic isnt the actual one , its just for testing , but the connector will stay like this ! Also i will now go back to the rockchip sbc for a short fixing !"}, {"post_id": 65576, "ts": "2026-09-10T20:14:37Z", "hours": 5.3633, "text": "I finally finished routing the board , some error hunting and silkscreen layout and its done !!! the 2 pwr layers are the turquoise and green"}, {"post_id": 63808, "ts": "2026-09-07T19:30:26Z", "hours": 2.8314, "text": "i did some further routing , i am now at the power routing and constrain regions etc…"}, {"post_id": 61825, "ts": "2026-09-04T22:32:22Z", "hours": 2.9669, "text": "Most of the signals (only 2-4 traces missing i think) are done and the ethernet is fixed… now only power and other stuff and its done !!! :)"}, {"post_id": 61716, "ts": "2026-09-04T19:11:48Z", "hours": 4.9678, "text": "I did a bunch of routing , everything from usb (includes redoing the usb3.0 stuff) , hdmi and mipi dsi and some other small stuff and fixes , and i found out that i am missing some parts like resistors at the ethernet schematic …"}, {"post_id": 60440, "ts": "2026-09-02T19:30:26Z", "hours": 2.7736, "text": "So today i decidet because stardance ends this month i dont have time for all the planned ideas , the mainboard is now some small features poorer like mipi csi cam port and sd but maybe i will add it back… but i changed some power parts and other things on the board . This will be the rough layout , its matched to sepperate power sections from high speed signals like form the ram , while having priority on fast signals and pheripherntials further away … Now that i think of it i will propably add an small glue spacer under the oled so it doesnt mess up any signals … The Fpga will now be a SOM module so i can make a devboard in the future while still use it in the detector panel wich i will make after the mainboard and som … Also i know the layout and parts placement etc is messy but this is just the rough layout as I said….."}, {"post_id": 59873, "ts": "2026-09-01T21:13:37Z", "hours": 0.25, "text": "A final change to the emmc , may logs i know but i didnt want the emmc to break the rest of the system so this is the final rev i hope !"}, {"post_id": 59866, "ts": "2026-09-01T20:54:41Z", "hours": 0.9836, "text": "I totally forgot about a signal layer so i redone the full design !"}, {"post_id": 59817, "ts": "2026-09-01T19:41:16Z", "hours": 2.5169, "text": "I addet the emmc routing , this was weirdly harder than the ram , to match the impedance i couldnt go between the bga pins and also they were pretty mixed up so i redid it some times and now its good ! All the importand to match in length signals are matched by impedance and trace length / distance to other tracks and via count …"}, {"post_id": 59107, "ts": "2026-08-31T18:53:32Z", "hours": 2.5003, "text": "i finally routed the lpddr4 with its different impedances , differential pairs , via and lentgh matching . The power traces will come later …"}, {"post_id": 58851, "ts": "2026-08-31T13:04:03Z", "hours": 1.0503, "text": "After much time i finally figured out how the reference desing uses such tiny trace width for the ddr routing . They had to use such small trace width to route it between the bga pins but that would not be the needet 80-100ohm impedance on the noncopular differential pair . The trick was they used a different trace spacing to archive around 120ohm +- toleranze ! I also have redone some of the bottom caps for easy routing and no interferance problems !"}, {"post_id": 58239, "ts": "2026-08-30T16:30:50Z", "hours": 2.0169, "text": "Today i routed many of the caps wich need to be under the rockchip for power filtering , if to far away it would cause an to high path inductance … it was a little tricky to get them all in place and not to near to each other … some caps will be around it on the pmic and other power sources as the bulk caps do not need to be near the pins always !"}, {"post_id": 57476, "ts": "2026-08-29T17:06:33Z", "hours": 6.6789, "text": "This was a really long routing session , on the way i changed some part sizes , and had some fun time (absolute hell) playing tetris with the ram ic , where what cap goes under or on the side of the ram . same for all of the different routing parts , also I saw that this will need an 8 layer board …"}, {"post_id": 56635, "ts": "2026-08-28T13:58:57Z", "hours": 1.5594, "text": "I started to do the layout of the Rockchip board , on the picture you can see the rockchip pmic , the bottom and top layer design is carefully considered for thermal and noise reduction . Also i swapped some components like cap footprint sizes where possible !"}, {"post_id": 54380, "ts": "2026-08-25T11:03:11Z", "hours": 2.0169, "text": "I found out that i had many caps way to big to fit under the rockchip (bottom pcb side), its essential for some caps to be near the pins in power domains like low voltage or any sensitive soc stuff … then i changed the caps manually 🫠 . I made a green box around bottom caps and then made the CSI adapter (eg. for a cam) , I cleaned up some schematics in sepperate pages . I connected some headders for gipos and uart/i2c and made the final schematic fixes and changes …. now the routing wich as you can see will be hell ! I almost forgot to mention i addet an small 0.9” spi tft . As you can see the schematic looks more like a neural network or spiderweb than routing , but atleast its not as bad as the fpga will be in routing !"}, {"post_id": 54313, "ts": "2026-08-25T08:14:30Z", "hours": 0.7333, "text": "Sadly i found out the rockchip only supports pcie in host mode , to i cant really make a pcie card from it but its not the end of the world , i removed the 12v power mux system and then addet an oculink adapter , the oculink will also be on the fpga devboard but with more than the rockchip x1 pcie … then i connected some pins , while also having the problem of finding 2 suitable pins on a 3.3v bank near the pcie !"}, {"post_id": 53192, "ts": "2026-08-23T17:05:51Z", "hours": 0.8, "text": "I connected many of the systems to the rockchip and did some datasheet reading to know how eg. the Pcie Interface is intendet to be made ont the Rockchip.."}, {"post_id": 53066, "ts": "2026-08-23T13:58:44Z", "hours": 0.45, "text": "I finished the USB-C new Connector and then made the 2Port Usb 2.0 , after that i addet an Usb 3.0 Port and used the design rules/constrains by the hardware design guide from Rockchip"}, {"post_id": 53052, "ts": "2026-08-23T13:24:51Z", "hours": 0.5167, "text": "You know the best about lookout , its bugs … i mean it nicely captured the hdmi schematic , i used the reference design form a rk3566 board and swapped the connector and some power things . But when i got to USB , wich includet swapping the USB-c to a right angle one for the Pcie card to save space , and adding a usb 2.0 (2 port) . I saw it didnt capture because some screen minimizing error … but its not the end of the world , it was just choosing an suitable usb c and swapping it with the old one , using the datasheet to find out the function of some pin circuitry in the reference design , and doing some brainstorming , i will add a female usb 3.0 port because i dont need the sata interface on the phy ! Also i addet a uart debug port.. and the usb c otg and pwr screenshot is unfinished as i will procced with a fresh lookout recording"}, {"post_id": 50363, "ts": "2026-08-19T15:17:01Z", "hours": 1.3836, "text": "I finished the PWR MUX , when pcie is used then it gets the 12v and 3.3v , that means the usb 5 to 3.3v and the 5v from usb cant be on at the same time , this power mux design wich was a headache because of many states and sometimes wierd graphs passes the 5v from usb to system and the 3.3v buck (from usb 5v) output to the system normally . When 12v is detected it disconnects these power lanes and activates an 12v to 5v buck aswell as the 3.3v from pcie is used then !"}, {"post_id": 47759, "ts": "2026-08-15T22:00:13Z", "hours": 0.3631, "text": "This was funny and dumb enough to be a reason for a journal . I compared some parts for the load switch (mux type) and when i picked one and looked at the datasheet i was confused for a good amount of time , turns out i was looking at a datasheet for a similar part and that explained why some things totally didnt match !"}, {"post_id": 46496, "ts": "2026-08-13T19:01:45Z", "hours": 1.3672, "text": "I started by connecting the ethernet IC to the rockchip , after that i started brainstorming and testing around wich pcie or oculink or similar i would use for the interconnect of the devboards . I decidet to make the rockchip devboard onto an pcie card , it can work as pcie or standalone wich in the end started a hunt for an good 2 channel P mosfet , because if pcie is used it gives me 12v(step down to 5v) and 3.3v so the 5v from usb isnt needet aswell as the 5 to 3.3v so i have to switch it off when the 12v is applied but thats smth for tomorrow"}, {"post_id": 46400, "ts": "2026-08-13T16:07:52Z", "hours": 0.8833, "text": "I made many modular sections of the devboard but still the actual connections to the rockchip were missing , i also had to rearange some pins , add buttons and testpoints and fix some wiring mistakes that came along the way!"}, {"post_id": 45840, "ts": "2026-08-12T15:49:50Z", "hours": 1.6822, "text": "It turned out for the Ethernet port i wont use the SDIO interface but MIIG , i used the RTL8211F-CG and a ethernet port with includet magnetics . This time there were no reference designs , and as i didnt want to go back and forth searching for the pins of this interface on the rockchip , I used AI to search for them and made a quick check if the Ai is telling false statements by manual checking !"}, {"post_id": 44653, "ts": "2026-08-10T15:46:41Z", "hours": 0.5503, "text": "I had to wait for this devlog , since lapse has a bug not seeing your hackatime projects , if you have the same problem just go to hackatime and paste your exact project name into the field and it will synch to it ! So i addet an micro sd slot and also started thinking about wifi , but as this rockchip mainboard will mostly be used in the ct scanner i will skip wifi and use ethernet instead , if you ask why not both ? Its because the sd card uses an SDIO bus and I only have 1 left avaible so its either ethernet or wifi or some unecessary option of both , in the ct scanner wifi would anyways be kinda unecessary !"}, {"post_id": 44065, "ts": "2026-08-09T16:10:39Z", "hours": 1.8361, "text": "After carefull consideration (rembering the zynq fpga series exist ..) I decidet to split the system onto 2 boards , a rockchp sbc and a kintex7 devboard like genysis2 from digilent but they can still work along over pcie thorugh octolink ! This time i removed the current sense ic , moved and changed hte rochip to a standalone board , while also changing its power input to usb-c . I addet the intendet to use 10.1 tft from lcsc with a connector for mipi-dsi and touch connector , luckily lcsc already has an reference schmetic for it so i dont have to map a connector and pins myself !"}, {"post_id": 15965, "ts": "2026-06-25T22:38:43Z", "hours": 1.2003, "text": "PWR Monitoring , today i thought its gonna be a fast finish but it totally wasnt .. i started chossing a current meter ic and there were many options eg. : hall effect but this isnt suitable for such a pcb , the routing and interference relally is not needet here , i originally planned to pick an current ic (1 channel with shunt circuit and i2c) but then i thought i have for the fpga part 4 rails i want to watch withouth interfereing with them , but the problem is that shunts at eg 1v20a full load would take to much W for my application from the bus … so i need small shunt values but some are too small for the ic to read and depending on ic have bad resolution .. So i picked for the 1v20a (most crutial rail) a 2.5mohm and for the rest a 5 ohm resistor .. Back to my solution , I went with a MICROCHIP PAC1934T-I/JQ (cheap , high stock and good specs , also has 4 channels wich is perfect !) , i hooked the circuit up after some datasheet and ref design reading and i am planning to maybe add another one to the board later for eg the usb of pcie pwr draw watching ! And also for the rockchip maybe but i will first have to check if the rockchips pmic already does it standalone .."}, {"post_id": 15353, "ts": "2026-06-24T23:26:02Z", "hours": 0.4644, "text": "Today i didnt really have time for any big changes so i just started to add some Shunt resistor (and finding suitable values) matching for the INA219 . I did this so that i can monitor the pwr rails of the fpga while running for any problems … and i dont really have a screenshot to show , this is a special tiny journal on a busy day !"}, {"post_id": 14597, "ts": "2026-06-23T19:21:28Z", "hours": 3.7414, "text": "SODIMM DDR3 is now finished ! , so this was reallyyyyyy easy , there was a reference and good section about it in the Kintex7 Fpga design NOTE , i picked a SODIMM 204Pin ddr3 slot and connected it to the fpga banks , some resistors and caps were necessary for the jedec standart but why did i even bother to use sodimm ddr3 ? , so i could go with ddr4 but the kintex7 tool for memory implementation isnt really and neither the speed made for it , also i took sodimm as i am able to easily swap the ram to other sizes or vendors , the pcb routing is way easier and ram modules can also be cheaper often then the bare ic for ddr3 … and the most importand part there is a eeprom on the modules containing the timing constrains !!!"}, {"post_id": 11405, "ts": "2026-06-18T17:46:00Z", "hours": 1.3, "text": "FPGA pwr Filter Caps selection… after the last journal i wanted to finally finish it so i went into the 7 Series FPGAs PCB Design Guide (UG483) , where cap values and count for the different FPGAs are listed , it went well other than searching for not in stock part alternatives (esr values are importand here and depending on cap listing there is no lcsc filter for it so i am going with good brands like murata and most popular filter and reading the datasheets till i find a fitting one ! ) … it defently wasnt so easy for the MGT pwr lines .. they are wayyyy more complicated and usecase depending ( https://docs.amd.com/v/u/en-US/ug476_7Series_Transceivers , or : https://docs.amd.com/v/u/en-US/ug471_7Series_SelectIO ) , but eventually i found a good middle between my needs and proven values from a ref. design . Lastly i addet the needet filter caps per FPGA bank and connected them up and thats it for this easy but redudant task !"}, {"post_id": 11361, "ts": "2026-06-18T16:04:46Z", "hours": 3.2839, "text": "Prog Page , so the schematic still needs sorting and all (not all off todays design is on the schem. page attached) … I finished the FT4232H circuit , then i started searching for a compatible flash from the PROG memory of the fpga , after pickcing one i made the circuit and proccedet to add a dip switch to select the fpga boot mode and connect the jtag from the FTDI ic … then i went over to make the USB-C circuit for the Rockchip and some of its filtering , afterwards i hocked up the FTDI to the debug port of the Rockchip . Lastly i addet the USB-C connector for the FTDI…"}, {"post_id": 10823, "ts": "2026-06-17T19:23:42Z", "hours": 2.1914, "text": "Usb Host , the Fpga needs an Jtag for programming and config + an uart for communication so i wanted to pick the mostly used FT2232H wich features 2 buses (for my case 1 jtag and 1 uart) . But then i thought while researching reference schematics , kintex7 and vivado compability and reading the datasheet , if i shouldnt just use an FT4232HL , but why that ? the rockchip also needs an uart for debug and i thought about adding a jtag but it turned out its internally , now the FT4232HL has 4 buses ’ 2 of them can do jtag and 2 uart (or other protocols btw) so i went with that and started designing it , took longer than expected as the eeprom selection and crystal isnt really troughout in the datasheet … so now i have an jtag and uart for the fpga , one for the rockchip debug and 1 additional port i will find a use for eventually … but the rockchip still needs an usb direct connection so it will get 2 usb c ports , a multiplexer isnt good here as it would prevent from using any fpga (or uart debug on rockchip) while doing otg (eg. flashing or other stuff ) .. Btw the screenshot is only a fraction of the schematic of it as stardance shows the boring part of the full screenshot so i cropped it"}, {"post_id": 10657, "ts": "2026-06-17T14:51:10Z", "hours": 1.9667, "text": "Finished Emmc Flash for Rockchip Soc , As the ddr4 is now finished i wanted to move on to the emmc flash , so i locked up the list of supported emmc parts but the list was from 2024 and had 2 model options for the RK3566 B/C but i had E??? So i was a little confused and began research but there was nothing so i scrapped the internet to find some newer list , eventually i found a updated one and there was a huge and i mean really huge list of tested emmc… I looked up wich ones are avaible on lcsc in my prefered GB size and picked one but after hooking up some connections i saw a problem , to use the H200 or H400 protocol speed like the rockchip wants VCCQ would need to be 1.8v but the datasheed meintion many times the chip can only work for 1 hour at a time then (also even finding the datasheet was hard) .. so i had to research and eventually found a better pick wich i hooked up and i changed the voltage config pins for the flash voltage on the rockchip addet some filters on the pwr lines and also hooked it up to the rockchip (not on the screenshot , other schem. page) .. there i addet the by the datasheet required parts and by the emmc datasheet …. also i addet a button to DAT0 , if this pin is connected to GND wich the button does when pressed the rockchip enters a failsafe mode .. this is a non brickable in soc safed mode that enables reflash/unbricking the soc over usb in case it happens (called Maskroom) …"}, {"post_id": 10210, "ts": "2026-06-16T20:37:35Z", "hours": 2.1667, "text": "Today i finished hooking up the lpddr4(later x) to the rockchip soc , but while doing so and following the offical ref. design and datasheet i saw a problem they were talking about CS0A/B and CS1A/B ??? So i was totally confused as that are not valid lpddr4 pins as far as i know it , so i proccedet to look at other projects schematics and i saw some using it too , but when i looked up the offical ref design and thier Ram’s Datasheets i saw that these pins arent real there too (so if i am not wrong they all used the ref design wich was for a specific ram or smth because on all designs the pins are NC or DNU pins so defently not connect !) .. But before i didnt know that i thought my ram that i planned to use (lpddr4) only had this problem as the datasheet says 1CS pin but after switching to s stlightly bigger (lpddr4x) type Ram i saw its the same 1cs per bank so anyways now i have an new ram and buck converter on the board 🫠… I will defently include a deeper note on this in the Github Repo ! The Buck is on another schematic page (not on the screenshot) , but it is just a standart SY8089AAAC making the 0.6V , note that its importand to pick an stable and fast switching buck for precision parts (fast or precise) like ram"}, {"post_id": 9965, "ts": "2026-06-16T14:28:44Z", "hours": 0.3758, "text": "Small Journal , i did the hardware block diagramm of the Helios One board , it simplifies how the ARM-Soc and the FPGA are connected , thier power systems and pheripherentials…"}, {"post_id": 9343, "ts": "2026-06-15T17:58:13Z", "hours": 11.2894, "text": "Old journals from Macondo , i noticed that this is a standalone projekt and i started this Pcb (new revision / total change of schematic) after 1 July so it fits .. (summarized old journals with Ai !): Summary of older Macondo journals because this project got moved over. The current revision of the board was started after 1 July and is a complete redesign around a Kintex7 FPGA and Rockchip SoC. I started by researching how to program the FPGA and looked at supported JTAG solutions. After comparing datasheets, reference designs and available parts on LCSC I decided to use an FT2232H based solution because it supports both JTAG and UART and has good performance, although I might still switch to an external low cost programmer later. One of the biggest architecture changes was switching from the original Rockchip choice to the RK3566. The larger Rockchip would have made routing on a 6 layer board extremely difficult and much more expensive. The RK3566 allows a cleaner and cheaper design while still supporting PCIe connectivity to the Kintex7 FPGA and MIPI DSI display output. A large amount of time was spent designing the FPGA power system. I studied datasheets, reference designs and power sequencing requirements to determine which rails could share supplies and where tighter ripple and tolerance requirements were needed. Special attention was required for the FPGA MGT transceiver power rails used for high speed interfaces such as PCIe. Many reference designs relied on unavailable or very expensive parts so I selected alternatives and redesigned the sequencing around the LM3881 supervisor. During this process I also designed the DDR and DDRVTT supplies and completed the entire FPGA power architecture. After finishing the FPGA side I moved on to the Rockchip power system. Using the datasheet and reference designs I adapted the design to remove unused functions while reusing parts already selected for the FPGA section to reduce BOM complexity and cost. I also had to replace an obsolete component with a software and hardware compatible alternative. Another sidequest was selecting suitable LPDDR4 memory. After checking the Rockchip memory requirements and available parts I found a low cost memory IC with two x16 dies, allowing it to satisfy the required x32 memory interface while remaining compatible with the platform. The memory power requirements were already provided by the Rockchip PMIC so no additional regulators were needed. Today I started placing the final filtering capacitors and connecting up the Rockchip section so that part is nearly finished. I also did some sidequests like determining pin requirements for the MIPI DSI display and Ethernet controller in preparation for the upcoming schematic work."}]...
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Title: Helios One by @Luka | Stardance
Devlogs:
O Title: Helios One by @Luka | Stardance
Devlogs:
Old journals from Macondo , i noticed that this is a standalone projekt and i started this Pcb (new revision / total change of schematic) after 1 July so it fits .. (summarized old journals with Ai !): Summary of older Macondo journals because this project got moved over. The current revision of the board was started after 1 July and is a complete redesign around a Kintex7 FPGA and Rockchip SoC. I started by researching how to program the FPGA and looked at supported JTAG solutions. After comparing datasheets, reference designs and available parts on LCSC I decided to use an FT2232H based solution because it supports both JTAG and UART and has good performance, although I might still switch to an external low cost programmer later. One of the biggest architecture changes was switching from the original Rockchip choice to the RK3566. The larger Rockchip would have made routing on a 6 layer board extremely difficult and much more expensive. The RK3566 allows a cleaner and cheaper design while still supporting PCIe connectivity to the Kintex7 FPGA and MIPI DSI display output. A large amount of time was spent designing the FPGA power system. I studied datasheets, reference designs and power sequencing requirements to determine which rails could share supplies and where tighter ripple and tolerance requirements were needed. Special attention was required for the FPGA MGT transceiver power rails used for high speed interfaces such as PCIe. Many reference designs relied on unavailable or very expensive parts so I selected alternatives and redesigned the sequencing around the LM3881 supervisor. During this process I also designed the DDR and DDRVTT supplies and completed the entire FPGA power architecture. After finishing the FPGA side I moved on to the Rockchip power system. Using the datasheet and reference designs I adapted the design to remove unused functions while reusing parts already selected for the FPGA section to reduce BOM complexity and cost. I also had to replace an obsolete component with a software and hardware compatible alternative. Another sidequest was selecting suitable LPDDR4 memory. After checking the Rockchip memory requirements and available parts I found a low cost memory IC with two x16 dies, allowing it to satisfy the required x32 memory interface while remaining compatible with the platform. The memory power requirements were already provided by the Rockchip PMIC so no additional regulators were needed. Today I started placing the final filtering capacitors and connecting up the Rockchip section so that part is nearly finished. I also did some sidequests like determining pin requirements for the MIPI DSI display and Ethernet controller in preparation for the upcoming schematic work.
Small Journal , i did the hardware block diagramm of the Helios One board , it simplifies how the ARM-Soc and the FPGA are connected , thier power systems and pheripherentials…
Today i finished hooking up the lpddr4(later x) to the rockchip soc , but while doing so and following the offical ref. design and datasheet i saw a problem they were talking about CS0A/B and CS1A/B ??? So i was totally confused as that are not valid lpddr4 pins as far as i know it , so i proccedet to look at other projects schematics and i saw some using it too , but when i looked up the offical ref design and thier Ram’s Datasheets i saw that these pins arent real there too (so if i am not wrong they all used the ref design wich was for a specific ram or smth because on all designs the pins are NC or DNU pins so defently not connect !) .. But before i didnt know that i thought my ram that i planned to use (lpddr4) only had this problem as the datasheet says 1CS pin but after switching to s stlightly bigger (lpddr4x) type Ram i saw its the same 1cs per bank so anyways now i have an new ram and buck converter on the board 🫠… I will defently include a deeper note on this in the Github Repo ! The Buck is on another schematic page (not on the screenshot) , but it is just a standart SY8089AAAC making the 0.6V , note that its importand to pick an stable and fast switching buck for precision parts (fast or precise) like ram
Finished Emmc Flash for Rockchip Soc , As the ddr4 is now finished i wanted to move on to the emmc flash , so i locked up the list of supported emmc parts but the list was from 2024 and had 2 model options for the RK3566 B/C but i had E??? So i was a little confused and began research but there was nothing so i scrapped the internet to find some newer list , eventually i found a updated one and there was a huge and i mean really huge list of tested emmc… I looked up wich ones are avaible on lcsc in my prefered GB size and picked one but after hooking up some connections i saw a problem , to use the H200 or H400 protocol speed like the rockchip wants VCCQ would need to be 1.8v but the datasheed meintion many times the chip can only work for 1 hour at a time then (also even finding the datasheet was hard) .. so i had to research and eventually found a better pick wich i hooked up and i changed the voltage config pins for the flash voltage on the rockchip addet some filters on the pwr lines and also hooked it up to the rockchip (not on the screenshot , other schem. page) .. there i addet the by the datasheet required parts and by the emmc datasheet …. also i addet a button to DAT0 , if this pin is connected to GND wich the button does when pressed the rockchip enters a failsafe mode .. this is a non brickable in soc safed mode that enables reflash/unbricking the soc over usb in case it happens (called Maskroom) …
Usb Host , the Fpga needs an Jtag for programming and config + an uart for communication so i wanted to pick the mostly used FT2232H wich features 2 buses (for my case 1 jtag and 1 uart) . But then i thought while researching reference schematics , kintex7 and vivado compability and reading the datasheet , if i shouldnt just use an FT4232HL , but why that ? the rockchip also needs an uart for debug and i thought about adding a jtag but it turned out its internally , now the FT4232HL has 4 buses ’ 2 of them can do jtag and 2 uart (or other protocols btw) so i went with that and started designing it , took longer than expected as the eeprom selection and crystal isnt really troughout in the datasheet … so now i have an jtag and uart for the fpga , one for the rockchip debug and 1 additional port i will find a use for eventually … but the rockchip still needs an usb direct connection so it will get 2 usb c ports , a multiplexer isnt good here as it would prevent from using any fpga (or uart debug on rockchip) while doing otg (eg. flashing or other stuff ) .. Btw the screenshot is only a fraction of the schematic of it as stardance shows the boring part of the full screenshot so i cropped it
Prog Page , so the schematic still needs sorting and all (not all off todays design is on the schem. page attached) … I finished the FT4232H circuit , then i started searching for a compatible flash from the PROG memory of the fpga , after pickcing one i made the circuit and proccedet to add a dip switch to select the fpga boot mode and connect the jtag from the FTDI ic … then i went over to make the USB-C circuit for the Rockchip and some of its filtering , afterwards i hocked up the FTDI to the debug port of the Rockchip . Lastly i addet the USB-C connector for the FTDI…
FPGA pwr Filter Caps selection… after the last journal i wanted to finally finish it so i went into the 7 Series FPGAs PCB Design Guide (UG483) , where cap values and count for the different FPGAs are listed , it went well other than searching for not in stock part alternatives (esr values are importand here and depending on cap listing there is no lcsc filter for it so i am going with good brands like murata and most popular filter and reading the datasheets till i find a fitting one ! ) … it defently wasnt so easy for the MGT pwr lines .. they are wayyyy more complicated and usecase depending ( https://docs.amd.com/v/u/en-US/ug476_7Series_Transceivers , or : https://docs.amd.com/v/u/en-US/ug471_7Series_SelectIO ) , but eventually i found a good middle between my needs and proven values from a ref. design . Lastly i addet the needet filter caps per FPGA bank and connected them up and thats it for this easy but redudant task !
SODIMM DDR3 is now finished ! , so this was reallyyyyyy easy , there was a reference and good section about it in the Kintex7 Fpga design NOTE , i picked a SODIMM 204Pin ddr3 slot and connected it to the fpga banks , some resistors and caps were necessary for the jedec standart but why did i even bother to use sodimm ddr3 ? , so i could go with ddr4 but the kintex7 tool for memory implementation isnt really and neither the speed made for it , also i took sodimm as i am able to easily swap the ram to other sizes or vendors , the pcb routing is way easier and ram modules can also be cheaper often then the bare ic for ddr3 … and the most importand part there is a eeprom on the modules containing the timing constrains !!!
Today i didnt really have time for any big changes so i just started to add some Shunt resistor (and finding suitable values) matching for the INA219 . I did this so that i can monitor the pwr rails of the fpga while running for any problems … and i dont really have a screenshot to show , this is a special tiny journal on a busy day !
PWR Monitoring , today i thought its gonna be a fast finish but it totally wasnt .. i started chossing a current meter ic and there were many options eg. : hall effect but this isnt suitable for such a pcb , the routing and interference relally is not needet here , i originally planned to pick an current ic (1 channel with shunt circuit and i2c) but then i thought i have for the fpga part 4 rails i want to watch withouth interfereing with them , but the problem is that shunts at eg 1v20a full load would take to much W for my application from the bus … so i need small shunt values but some are too small for the ic to read and depending on ic have bad resolution .. So i picked for the 1v20a (most crutial rail) a 2.5mohm and for the rest a 5 ohm resistor .. Back to my solution , I went with a MICROCHIP PAC1934T-I/JQ (cheap , high stock and good specs , also has 4 channels wich is perfect !) , i hooked the circuit up after some datasheet and ref design reading and i am planning to maybe add another one to the board later for eg the usb of pcie pwr draw watching ! And also for the rockchip maybe but i will first have to check if the rockchips pmic already does it standalone ..
After carefull consideration (rembering the zynq fpga series exist ..) I decidet to split the system onto 2 boards , a rockchp sbc and a kintex7 devboard like genysis2 from digilent but they can still work along over pcie thorugh octolink ! This time i removed the current sense ic , moved and changed hte rochip to a standalone board , while also changing its power input to usb-c . I addet the intendet to use 10.1 tft from lcsc with a connector for mipi-dsi and touch connector , luckily lcsc already has an reference schmetic for it so i dont have to map a connector and pins myself !
I had to wait for this devlog , since lapse has a bug not seeing your hackatime projects , if you have the same problem just go to hackatime and paste your exact project name into the field and it will synch to it ! So i addet an micro sd slot and also started thinking about wifi , but as this rockchip mainboard will mostly be used in the ct scanner i will skip wifi and use ethernet instead , if you ask why not both ? Its because the sd card uses an SDIO bus and I only have 1 left avaible so its either ethernet or wifi or some unecessary option of both , in the ct scanner wifi would anyways be kinda unecessary !
It turned out for the Ethernet port i wont use the SDIO interface but MIIG , i used the RTL8211F-CG and a ethernet port with includet magnetics . This time there were no reference designs , and as i didnt want to go back and forth searching for the pins of this interface on the rockchip , I used AI to search for them and made a quick check if the Ai is telling false statements by manual checking !
I made many modular sections of the devboard but still the actual connections to the rockchip were missing , i also had to rearange some pins , add buttons and testpoints and fix some wiring mistakes that came along the way!
I started by connecting the ethernet IC to the rockchip , after that i started brainstorming and testing around wich pcie or oculink or similar i would use for the interconnect of the devboards . I decidet to make the rockchip devboard onto an pcie card , it can work as pcie or standalone wich in the end started a hunt for an good 2 channel P mosfet , because if pcie is used it gives me 12v(step down to 5v) and 3.3v so the 5v from usb isnt needet aswell as the 5 to 3.3v so i have to switch it off when the 12v is applied but thats smth for tomorrow
This was funny and dumb enough to be a reason for a journal . I compared some parts for the load switch (mux type) and when i picked one and looked at the datasheet i was confused for a good amount of time , turns out i was looking at a datasheet for a similar part and that explained why some things totally didnt match !
I finished the PWR MUX , when pcie is used then it gets the 12v and 3.3v , that means the usb 5 to 3.3v and the 5v from usb cant be on at the same time , this power mux design wich was a headache because of many states and sometimes wierd graphs passes the 5v from usb to system and the 3.3v buck (from usb 5v) output to the system normally . When 12v is detected it disconnects these power lanes and activates an 12v to 5v buck aswell as the 3.3v from pcie is used then !
You know the best about lookout , its bugs … i mean it nicely captured the hdmi schematic , i used the reference design form a rk3566 board and swapped the connector and some power things . But when i got to USB , wich includet swapping the USB-c to a right angle one for the Pcie card to save space , and adding a usb 2.0 (2 port) . I saw it didnt capture because some screen minimizing error … but its not the end of the world , it was just choosing an suitable usb c and swapping it with the old one , using the datasheet to find out the function of some pin circuitry in the reference design , and doing some brainstorming , i will add a female usb 3.0 port because i dont need the sata interface on the phy ! Also i addet a uart debug port.. and the usb c otg and pwr screenshot is unfinished as i will procced with a fresh lookout recording
I finished the USB-C new Connector and then made the 2Port Usb 2.0 , after that i addet an Usb 3.0 Port and used the design rules/constrains by the hardware design guide from Rockchip
I connected many of the systems to the rockchip and did some datasheet reading to know how eg. the Pcie Interface is intendet to be made ont the Rockchip..
Sadly i found out the rockchip only supports pcie in host mode , to i cant really make a pcie card from it but its not the end of the world , i removed the 12v power mux system and then addet an oculink adapter , the oculink will also be on the fpga devboard but with more than the rockchip x1 pcie … then i connected some pins , while also having the problem of finding 2 suitable pins on a 3.3v bank near the pcie !
I found out that i had many caps way to big to fit under the rockchip (bottom pcb side), its essential for some caps to be near the pins in power domains like low voltage or any sensitive soc stuff … then i changed the caps manually 🫠 . I made a green box around bottom caps and then made the CSI adapter (eg. for a cam) , I cleaned up some schematics in sepperate pages . I connected some headders for gipos and uart/i2c and made the final schematic fixes and changes …. now the routing wich as you can see will be hell ! I almost forgot to mention i addet an small 0.9” spi tft . As you can see the schematic looks more like a neural network or spiderweb than routing , but atleast its not as bad as the fpga will be in routing !
I started to do the layout of the Rockchip board , on the picture you can see the rockchip pmic , the bottom and top layer design is carefully considered for thermal and noise reduction . Also i swapped some components like cap footprint sizes where possible !
This was a really long routing session , on the way i changed some part sizes , and had some fun time (absolute hell) playing tetris with the ram ic , where what cap goes under or on the side of the ram . same for all of the different routing parts , also I saw that this will need an 8 layer board …
Today i routed many of the caps wich need to be under the rockchip for power filtering , if to far away it would cause an to high path inductance … it was a little tricky to get them all in place and not to near to each other … some caps will be around it on the pmic and other power sources as the bulk caps do not need to be near the pins always !
After much time i finally figured out how the reference desing uses such tiny trace width for the ddr routing . They had to use such small trace width to route it between the bga pins but that would not be the needet 80-100ohm impedance on the noncopular differential pair . The trick was they used a different trace spacing to archive around 120ohm +- toleranze ! I also have redone some of the bottom caps for easy routing and no interferance problems !
i finally routed the lpddr4 with its different impedances , differential pairs , via and lentgh matching . The power traces will come later …
I addet the emmc routing , this was weirdly harder than the ram , to match the impedance i couldnt go between the bga pins and also they were pretty mixed up so i redid it some times and now its good ! All the importand to match in length signals are matched by impedance and trace length / distance to other tracks and via count …
I totally forgot about a signal layer so i redone the full design !
A final change to the emmc , may logs i know but i didnt want the emmc to break the rest of the system so this is the final rev i hope !
So today i decidet because stardance ends this month i dont have time for all the planned ideas , the mainboard is now some small features poorer like mipi csi cam port and sd but maybe i will add it back… but i changed some power parts and other things on the board . This will be the rough layout , its matched to sepperate power sections from high speed signals like form the ram , while having priority on fast signals and pheripherntials further away … Now that i think of it i will propably add an small glue spacer under the oled so it doesnt mess up any signals … The Fpga will now be a SOM module so i can make a devboard in the future while still use it in the detector panel wich i will make after the mainboard and som … Also i know the layout and parts placement etc is messy but this is just the rough layout as I said…..
I did a bunch of routing , everything from usb (includes redoing the usb3.0 stuff) , hdmi and mipi dsi and some other small stuff and fixes , and i found out that i am missing some parts like resistors at the ethernet schematic …
Most of the signals (only 2-4 traces missing i think) are done and the ethernet is fixed… now only power and other stuff and its done !!! :)
i did some further routing , i am now at the power routing and constrain regions etc…
I finally finished routing the board , some error hunting and silkscreen layout and its done !!! the 2 pwr layers are the turquoise and green
After doing the rockchip sbc , i started with the fpga som , i will redo the power parts as i switched to a fpga (same model) with less pins , and a small package … i laso installed vivado wich totally hanged up my pc so i had to pause work , i needet to do it to get the pinout for the ddr3 to fpga (MIG = memory interface generator wizard) . The layout on the pic isnt the actual one , its just for testing , but the connector will stay like this ! Also i will now go back to the rockchip sbc for a short fixing !
I updates some parts , mostly cap placement because it was to crowdet and i made an export of the layers … https://github.com/Luka-io/RadiaX/blob/main/electronics/layers.pdf
I used the Mig Interface pin xdc file i created to connect the ddr3 to the fpga banks and then made the power interface for it !
The fpga SOM , PWR system is now finished . I already had the old power system but now its an smaller fpga package and power requirements , so i cleaned up suitable parts , let ai compare some dc/dc board mounts to safe space , designed some power sections and conmbined them all , etc…
THXXXX for the SUPER STAR !!!!! I finished the PWR filtering , i had to add some filter caps on the DDR3 . Then i used the LiteX Repo to see if i should add an EMMC , i decidet against it because of cost (already a problem…) and space constrains . But still i had to redo the Prog. section (mostly bank0 on the Kintex7) again because i accedently deleted it many journals ago when i sepperated the rockchip and kintex ! I went with a SPI flash (quad spi) … then I connected some mandatory config and other circuitry , this was mostly straightforward with the ref. designs and the ABSOLUTELY many documents on the AMD Technical Information Portal
The fpga SOM is now almost done , this was a faster pcb than i expected , i know it may look messy and crowdet but the pwr stuff is actually layouted in the best possible way(atleast i hope so) and some other things , now only some schematic finishing and checking is needet , then I can route and finish it !
I finished the Layout of the FPGA SOM , the filter caps have a really high footprint so that was tricky and the vtt resistors for the ddr3 , its a asingle ddr3 ic so that was weird …
So marco made the Kintex Fpga a 3d model , there werent any good ones out there … Its the big metal thingy you can see in the middle of the Pcb . He send me the wrong footprint to installed freecad and resized it (I like fusion360 but i dont have it installed on my new laptop..) , Also I rendered the Pcb in blender ! I know the routing isnt finished but i really dont have the energie and time for it today !
SO the devlog may seem long… but i lost 2 hours of footage while routing so yeah .. i routed the ddr3 , that includes the diff pairs , length matching and impedance constrains , etc … bla bla bla tech stuff , this took longer and was harder than the double stack (2 ics in one) lpddr4 on the rockchip board , idk why , propably placement and fpgas being tricky in general !
The SOM was wayyy to expensive for the 600 dollar funding limit … so i had to choose an smaller LUTS fpga model and for it change the recommendet decoupling caps amount . Afterwards I changed some parts for cost saving and played around with coupons till it fit the 600 dollar funding limit … .. .
Long time no devlog but its just power routing and some tricky layout changes . The only sad part to switch from the kintex7 325T to a smaller variant , same for the ram …. funding 600$ cap :,)
My Last designing Devlog , its been a reallyyyyy long part of the project RadiaX but the FPGA SOM , aswell as the rockchip sbc are finished ! (wich is more of an placeholder rg , because the funding does not make it possible… ) I am happy to ship it NOW !
I totally forgot to add Testpoints haha , now there are some on the PWR rails !...
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Desktop To-do list Widget by @LaraCroft | Stardanc Desktop To-do list Widget by @LaraCroft | Stardance...
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My very own WebOS by @Sanvi_K | Stardance
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[{"post_id": 23994, "ts": "202 [{"post_id": 23994, "ts": "2026-07-07T08:22:45Z", "hours": 1.8472, "text": "Decorated my Clothing WebOS a little more! I spent FOREVER trying to get the time element and background to work. It’s going good so far though, and soon you guys can try it out!"}, {"post_id": 23357, "ts": "2026-07-06T08:50:23Z", "hours": 1.7103, "text": "I’m making a high school clothing guide WebOS for both girls and guys. It’s going great! I’ve done the first section of the guide and half of the second. I’ve put text, images, links and borders and will work on styling it. I want to add pages where I can separate Y2K clothes from clean girl outfits, Budget friendly from more expensive and possibly make a ‘wardrobe’ section where people can choose outfits they like and the web will give them more outfits based on a test. I don’t know if I can do that, but I will try!"}]...
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Title: My very own WebOS by @Sanvi_K | Stardance
Title: My very own WebOS by @Sanvi_K | Stardance
Devlogs:
I’m making a high school clothing guide WebOS for both girls and guys. It’s going great! I’ve done the first section of the guide and half of the second. I’ve put text, images, links and borders and will work on styling it. I want to add pages where I can separate Y2K clothes from clean girl outfits, Budget friendly from more expensive and possibly make a ‘wardrobe’ section where people can choose outfits they like and the web will give them more outfits based on a test. I don’t know if I can do that, but I will try!
Decorated my Clothing WebOS a little more! I spent FOREVER trying to get the time element and background to work. It’s going good so far though, and soon you guys can try it out!...
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sniff-the-bag.ai by @nobrainerparikshit | Stardanc sniff-the-bag.ai by @nobrainerparikshit | Stardance...
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My awesome macropad! by @sandyh12812 | Stardance
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TuneDeck: A Wi-Fi Enabled Physical Media Controlle TuneDeck: A Wi-Fi Enabled Physical Media Controller for Spotify by @anshpatel9720 | Stardance...
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[{"post_id": 10170, "ts": "202 [{"post_id": 10170, "ts": "2026-06-16T19:42:18Z", "hours": 0.4603, "text": "now i m working on build in wokwi so i now which component is best for my project."}]...
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Title: TuneDeck: A Wi-Fi Enabled Physical Media Co Title: TuneDeck: A Wi-Fi Enabled Physical Media Controller for Spotify by @anshpatel9720 | Stardance
Devlogs:
now i m working on build in wokwi so i now which component is best for my project....
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My very own WebOS by @Aadarsh | Stardance
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My awesome macropad! by @sandyh12812 | Stardance
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My awesome macropad! by @otiliamuntean48 | Stardan My awesome macropad! by @otiliamuntean48 | Stardance...
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Title: My awesome macropad! by @otiliamuntean48 | Title: My awesome macropad! by @otiliamuntean48 | Stardance...
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RhythmCremental by @OrangePainting | Stardance
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[{"post_id": 9622, "ts": "2026 [{"post_id": 9622, "ts": "2026-06-16T00:50:57Z", "hours": 1.5153, "text": "This is a game I am working on that combines both rhythm and incremental genres to make something that remains fun over time. Currently, I am reworking my core mechanic as it doesn’t feel as fun as I want it. I’m experimenting with a match 3 mechanic to hopefully get some fun gameplay!"}]...
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Title: RhythmCremental by @OrangePainting | Starda Title: RhythmCremental by @OrangePainting | Stardance
Devlogs:
This is a game I am working on that combines both rhythm and incremental genres to make something that remains fun over time. Currently, I am reworking my core mechanic as it doesn’t feel as fun as I want it. I’m experimenting with a match 3 mechanic to hopefully get some fun gameplay!...
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Exploring the Moon with Artemis Website by @Lidika Exploring the Moon with Artemis Website by @LidikaRahman | Stardance...
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[{"ship_num": 1, "ts": "2026-0 [{"ship_num": 1, "ts": "2026-06-30T18:19:22Z", "hours": 9.0, "multiplier": null, "payout": 0, "blessing": "neutral", "text": "This week, the project took a big step forward. I began building the SLS Engineering section, where users won’t just read about NASA’s rocket, in fact they’ll build an understanding of it through a 12-stage launch simulation. The biggest challenge was the JavaScript behind the scenes. Every launch stage happens within seconds, so keeping the timing and calculations synchronized turned out to be much harder than I expected. After many failed attempts, I realized the problem wasn’t the math itself, rather it was when the calculations were being updated. Once I fixed that logic, everything finally worked as intended. As I continue building, I’m thinking carefully about the quality-of-life problem this project solves. Space science is often taught through long videos or textbook diagrams, making it difficult for many students to stay engaged or understand how everything connects in a real mission. My goal is to remove that friction by turning complex STEM concepts into an interactive experience where students actively participate instead of passively reading. The next stages will introduce astronaut engineering challenges, real-time mission mathematics, rocket fueling, launch operations, Moon landing procedures, scientific experiments, and mission decision-making. Every activity is designed to mirror real Artemis-inspired workflows while providing instant feedback, progress tracking, and personalized learning. Instead of simply learning about a mission, users gradually build the confidence and practical understanding to think like an engineer, scientist, and astronaut. The goal is simple: make learning space exploration more interactive, more intuitive, and far more memorable.", "repo": "https://github.com/LidikaRahman2023/moon-exploration-artemis", "demo": "https://lidikarahman2023.github.io/moon-exploration-artemis/"}]...
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[{"post_id": 19389, "ts": "202 [{"post_id": 19389, "ts": "2026-06-30T18:10:12Z", "hours": 6.0333, "text": "Exploring the Moon with Artemis!— Dev Log #3✅ What I Added: Started building the SLS Engineering section. Added the foundation for the 12-stage launch simulation. Challenges I faced: The JavaScript was the hardest part.Since each stage changes within seconds, handling the timings and calculations became more complex than I expected.Ran into repeated errors before finding the real issue. What I Learned: Improved my understanding of JavaScript timing and calculation logic.Sometimes the bug isn’t in the formula, and it’s in how and when it’s being updated. An important decision I made : Chose to break the launch into 12 interactive stages instead of one animation, making it more engaging and educational. ✨ Progress: Finally figured out the calculation loophole, and everything is working much more smoothly now. One step closer to launching Artemis! 🌙🚀"}, {"post_id": 11548, "ts": "2026-06-18T20:53:05Z", "hours": 2.3611, "text": "Exploring the Moon with Artemis! — Dev Log #2 What I built : • Added astronaut gender selection. • Added the dashboard introduction section. The Challenges I faced : •Faced some annoying alignment issues. •Had a bug where selections weren’t updating correctly. What I’ve Learned: • Better understanding of handling user selections and progress tracking. Decision I made: Started with astronaut personalization before the missions.Makes the experience feel more personal from the start. Something that SURPRISED me: The dashboard already makes the project feel like a real astronaut training platform! And about the Design: Going for a fun, friendly space theme while keeping the Artemis mission feeling realistic. Next up: astronaut training and mission systems!"}, {"post_id": 10070, "ts": "2026-06-16T17:28:03Z", "hours": 0.9944, "text": "My today’s update tackles user friction head-on by introducing a “Continue as Guest” option, allowing people to bypass the sign-up gate and dive straight into my project. To match this seamless flow, I gave the resident astronaut mascot a major upgrade; it now dynamically changes its greeting for guest users and delivers a revamped introductory speech that clearly lays out my mission, the problem statement, and the core solution right from the launchpad."}]...
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Title: Exploring the Moon with Artemis Website by Title: Exploring the Moon with Artemis Website by @LidikaRahman | Stardance
Devlogs:
My today’s update tackles user friction head-on by introducing a “Continue as Guest” option, allowing people to bypass the sign-up gate and dive straight into my project. To match this seamless flow, I gave the resident astronaut mascot a major upgrade; it now dynamically changes its greeting for guest users and delivers a revamped introductory speech that clearly lays out my mission, the problem statement, and the core solution right from the launchpad.
Exploring the Moon with Artemis! — Dev Log #2 What I built : • Added astronaut gender selection. • Added the dashboard introduction section. The Challenges I faced : •Faced some annoying alignment issues. •Had a bug where selections weren’t updating correctly. What I’ve Learned: • Better understanding of handling user selections and progress tracking. Decision I made: Started with astronaut personalization before the missions.Makes the experience feel more personal from the start. Something that SURPRISED me: The dashboard already makes the project feel like a real astronaut training platform! And about the Design: Going for a fun, friendly space theme while keeping the Artemis mission feeling realistic. Next up: astronaut training and mission systems!
Exploring the Moon with Artemis!— Dev Log #3✅ What I Added: Started building the SLS Engineering section. Added the foundation for the 12-stage launch simulation. Challenges I faced: The JavaScript was the hardest part.Since each stage changes within seconds, handling the timings and calculations became more complex than I expected.Ran into repeated errors before finding the real issue. What I Learned: Improved my understanding of JavaScript timing and calculation logic.Sometimes the bug isn’t in the formula, and it’s in how and when it’s being updated. An important decision I made : Chose to break the launch into 12 interactive stages instead of one animation, making it more engaging and educational. ✨ Progress: Finally figured out the calculation loophole, and everything is working much more smoothly now. One step closer to launching Artemis! 🌙🚀
Ships:
This week, the project took a big step forward. I began building the SLS Engineering section, where users won’t just read about NASA’s rocket, in fact they’ll build an understanding of it through a 12-stage launch simulation. The biggest challenge was the JavaScript behind the scenes. Every launch stage happens within seconds, so keeping the timing and calculations synchronized turned out to be much harder than I expected. After many failed attempts, I realized the problem wasn’t the math itself, rather it was when the calculations were being updated. Once I fixed that logic, everything finally worked as intended. As I continue building, I’m thinking carefully about the quality-of-life problem this project solves. Space science is often taught through long videos or textbook diagrams, making it difficult for many students to stay engaged or understand how everything connects in a real mission. My goal is to remove that friction by turning complex STEM concepts into an interactive experience where students actively participate instead of passively reading. The next stages will introduce astronaut engineering challenges, real-time mission mathematics, rocket fueling, launch operations, Moon landing procedures, scientific experiments, and mission decision-making. Every activity is designed to mirror real Artemis-inspired workflows while providing instant feedback, progress tracking, and personalized learning. Instead of simply learning about a mission, users gradually build the confidence and practical understanding to think like an engineer, scientist, and astronaut. The goal is simple: make learning space exploration more interactive, more intuitive, and far more memorable....
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1793886850.5795467
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1793973250.5795467
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19284
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HW project thing by @Anson | Stardance
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Anson
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0
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0.0
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0
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[]
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[]
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Title: HW project thing by @Anson | Stardance
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1793512515.647292
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1794117315.647292
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19285
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Orbit-Chroma-9 by @Mrolypath | Stardance
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Mrolypath
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0
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2.44
|
0
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[]
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[{"post_id": 14679, "ts": "202 [{"post_id": 14679, "ts": "2026-06-23T21:23:59Z", "hours": 2.4394, "text": "Orbit-Chroma-9 Devlog #1: Schematic Done, Moving to PCB Layout The Vision I’m building a 9-key mechanical macro pad powered by a Seeeduino XIAO. I’m planning to include an I2C OLED screen (hoping to get live Bongo Cat animations running on it!), a rotary encoder knob for volume control, and addressable RGB LEDs for underglow backlighting. The Journey So Far 1. Fixing the Matrix Math Since the Seeeduino XIAO doesn’t have a ton of GPIO pins, I couldn’t connect all 9 switches directly. Instead, I wired them into a 3x3 keyboard matrix. This lets me scan all 9 keys using just 6 pins, which leaves the remaining pins open to run the OLED display screen without running out of IO. 2. Adding Diodes To make sure the keys register properly when pressed at the same time, I added a switching diode to every switch. They act like one-way valves to prevent ghosting when holding down multiple keys. 3. Hardware Add-ons I’m adding three main features to the board: Rotary Encoder (SW10): An infinite spinning knob that handles volume control by tracking internal switch pulses. OLED Screen (J1): A tiny screen for animations that runs on I2C communication, meaning it only uses two lines (SDA and SCL) instead of a massive bundle of wires. RGB LEDs: Daisy-chained NeoPixels that share a single data pin to control color and brightness individually. Roadblocks & Lessons Learned The Grid and Spaghetti Wire Mess: When I first started drawing connections in KiCad, it turned into a massive spiderweb of overlapping green lines. To make it worse, my grid settings were mismatched, so wires looked crooked and wouldn’t snap onto the component pins. I fixed it by resetting my grid snap, wiping the messy wires, and using Global Labels instead of drawing lines across the whole page. It looks way more professional now. Diode Orientation: Placing 9 diodes in a tight grid got confusing, and I realized halfway through that I mixed up the direction on a few of them. If they face the wrong way, the switch breaks because current can’t flow back to the row pins. I had to look closely at the symbols and flip them so they all match. Missing XIAO Footprint: KiCad’s Electrical Rules Checker threw an error because it couldn’t find a built-in footprint for the Seeeduino XIAO. After doing some research, I swapped it for a standard DIP-14 footprint. Since it shares the exact same 2.54mm pin spacing, the physical board will line up perfectly and the XIAO can slide right in. What’s Next Now that the schematic is done, I’m hitting ‘F8’ to pull all the components over into the 2D PCB editor canvas. Next up is the hard part: routing the physical copper lines without letting them cross each other!"}]...
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Title: Orbit-Chroma-9 by @Mrolypath | Stardance
D Title: Orbit-Chroma-9 by @Mrolypath | Stardance
Devlogs:
Orbit-Chroma-9 Devlog #1: Schematic Done, Moving to PCB Layout The Vision I’m building a 9-key mechanical macro pad powered by a Seeeduino XIAO. I’m planning to include an I2C OLED screen (hoping to get live Bongo Cat animations running on it!), a rotary encoder knob for volume control, and addressable RGB LEDs for underglow backlighting. The Journey So Far 1. Fixing the Matrix Math Since the Seeeduino XIAO doesn’t have a ton of GPIO pins, I couldn’t connect all 9 switches directly. Instead, I wired them into a 3x3 keyboard matrix. This lets me scan all 9 keys using just 6 pins, which leaves the remaining pins open to run the OLED display screen without running out of IO. 2. Adding Diodes To make sure the keys register properly when pressed at the same time, I added a switching diode to every switch. They act like one-way valves to prevent ghosting when holding down multiple keys. 3. Hardware Add-ons I’m adding three main features to the board: Rotary Encoder (SW10): An infinite spinning knob that handles volume control by tracking internal switch pulses. OLED Screen (J1): A tiny screen for animations that runs on I2C communication, meaning it only uses two lines (SDA and SCL) instead of a massive bundle of wires. RGB LEDs: Daisy-chained NeoPixels that share a single data pin to control color and brightness individually. Roadblocks & Lessons Learned The Grid and Spaghetti Wire Mess: When I first started drawing connections in KiCad, it turned into a massive spiderweb of overlapping green lines. To make it worse, my grid settings were mismatched, so wires looked crooked and wouldn’t snap onto the component pins. I fixed it by resetting my grid snap, wiping the messy wires, and using Global Labels instead of drawing lines across the whole page. It looks way more professional now. Diode Orientation: Placing 9 diodes in a tight grid got confusing, and I realized halfway through that I mixed up the direction on a few of them. If they face the wrong way, the switch breaks because current can’t flow back to the row pins. I had to look closely at the symbols and flip them so they all match. Missing XIAO Footprint: KiCad’s Electrical Rules Checker threw an error because it couldn’t find a built-in footprint for the Seeeduino XIAO. After doing some research, I swapped it for a standard DIP-14 footprint. Since it shares the exact same 2.54mm pin spacing, the physical board will line up perfectly and the XIAO can slide right in. What’s Next Now that the schematic is done, I’m hitting ‘F8’ to pull all the components over into the 2D PCB editor canvas. Next up is the hard part: routing the physical copper lines without letting them cross each other!...
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1793382482.2028816
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1793987282.2028816
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19286
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Hardware is hard by @clayanicholson | Stardance
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clayanicholson
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0
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0.0
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0
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[]
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[]
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Title: Hardware is hard by @clayanicholson | Stard Title: Hardware is hard by @clayanicholson | Stardance...
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1793965664.8518388
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1794570464.8518388
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19287
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My very own WebOS by @maxoliver | Stardance
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maxoliver
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0
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0.0
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0
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[]
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[]
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Title: My very own WebOS by @maxoliver | Stardance
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1793569937.272587
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1794174737.272587
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19288
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Children's Business Fair Website by @anish17 | Children's Business Fair Website by @anish17 | Stardance...
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anish17
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1
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2.65
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0
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[{"ship_num": 1, "ts": "2026-0 [{"ship_num": 1, "ts": "2026-06-15T18:16:12Z", "hours": 1.0, "multiplier": null, "payout": 0, "blessing": "neutral", "text": "I developed a website for the Children’s Business Fair. I have been working for multiple months and am proud to launch it. The Naperville Children’s Business Fair supports young entrepreneurs in the Chicagoland community and we are proud to have a website for the 2026 season.", "repo": "https://github.com/anishshah17/cbf-websitev1", "demo": "https://napervillecbf.com"}]...
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[{"post_id": 33630, "ts": "202 [{"post_id": 33630, "ts": "2026-07-23T18:21:38Z", "hours": 1.6536, "text": "CBF Website Update"}, {"post_id": 9351, "ts": "2026-06-15T18:07:51Z", "hours": 1.0111, "text": "I am working on adding an about page to the website!"}]...
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Title: Children's Business Fair Website by @an Title: Children's Business Fair Website by @anish17 | Stardance
Devlogs:
I am working on adding an about page to the website!
CBF Website Update
Ships:
I developed a website for the Children’s Business Fair. I have been working for multiple months and am proud to launch it. The Naperville Children’s Business Fair supports young entrepreneurs in the Chicagoland community and we are proud to have a website for the 2026 season....
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1793951485.4633582
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1794037885.4633582
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19289
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Untitled project by @jaketorohopkins | Stardance
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jaketorohopkins
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0
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0.0
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0
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[]
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[]
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Title: Untitled project by @jaketorohopkins | Star Title: Untitled project by @jaketorohopkins | Stardance...
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1793530134.1200912
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1794134934.1200912
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19290
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Baby's first numerical library by @cebula | St Baby's first numerical library by @cebula | Stardance...
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cebula
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0
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0.0
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0
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[]
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[]
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Title: Baby's first numerical library by @cebu Title: Baby's first numerical library by @cebula | Stardance...
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1793372037.8455849
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1793976837.8455849
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19291
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Pixel RPG by @Saveer | Stardance
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Saveer
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0
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0.0
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0
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[]
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[]
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Title: Pixel RPG by @Saveer | Stardance
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1793436586.458255
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1794041386.458255
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19292
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Meowpad by @asherm | Stardance
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asherm
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0
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0.0
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0
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[]
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[]
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Title: Meowpad by @asherm | Stardance
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1793447288.4916897
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1794311288.4916897
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19293
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GLAP by @GameLord2011 | Stardance
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GameLord2011
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3
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59.0
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707
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[{"ship_num": 1, "ts": "2026-1 [{"ship_num": 1, "ts": "2026-10-28T22:36:07Z", "hours": 6.0, "multiplier": 15.36, "payout": 99, "blessing": "neutral", "text": "I added a visualizer, learned a timing method, and squashed various bugs.", "repo": "https://github.com/GameLord2011/GLAP", "demo": "https://github.com/GameLord2011/GLAP/releases/tag/3.0.0"}, {"ship_num": 2, "ts": "2026-08-29T19:56:06Z", "hours": 19.0, "multiplier": 18.61, "payout": 360, "blessing": "neutral", "text": "I added configuration. I learned how serialization and deserialization work. I also learned how to document things. Thanks for everyone that helped with my project. Here’s an example theme to get you started with theming ([PHOTOSENSITIVE EPILEPISY WARNING]; also it doesn’t work on terminal.app because Apple is mean): [ theme ] background = \"#b8d60e\" foreground = \"#ff00ff\" controls = \"#5f4808\" playbar = \"#00fff2\"", "repo": "https://github.com/GameLord2011/GLAP", "demo": "https://github.com/GameLord2011/GLAP/releases/tag/3.0.0"}, {"ship_num": 3, "ts": "2026-08-02T17:09:50Z", "hours": 34.0, "multiplier": 7.33, "payout": 248, "blessing": "neutral", "text": "I basically made a TUI music player app in Rust, in the process learning how structs, ownership, threads, callbacks, and a bunch of other Rust things work. The hardest part was setting up the state handling. I am really proud of how this ended up.", "repo": "https://github.com/GameLord2011/GLAP", "demo": "https://github.com/GameLord2011/GLAP/releases/tag/3.0.0"}]...
|
[{"post_id": 83932, "ts": "202 [{"post_id": 83932, "ts": "2026-10-28T22:24:41Z", "hours": 6.4611, "text": "I added an audio graph and did some very many refactors."}, {"post_id": 57593, "ts": "2026-08-29T19:51:55Z", "hours": 0.4047, "text": "22 mins of trying and failing to convert it to sdl3. sdl2 forever"}, {"post_id": 57562, "ts": "2026-08-29T18:56:46Z", "hours": 0.8017, "text": "Added some doc comments because I plan to at some point have the audio-handling junk in a seperate crate so you can staple a frontend onto it. Okie now I can do v2.0"}, {"post_id": 56306, "ts": "2026-08-28T01:19:39Z", "hours": 2.8594, "text": "Bump version, and do a boatload of under-the-hood microoptimizations and horribly unreadable code paired with next-to-no docs."}, {"post_id": 54051, "ts": "2026-08-24T20:16:03Z", "hours": 1.1808, "text": "I did some general stability improvments and added error handling for the config (thanks @tkrl for bringing that to light)."}, {"post_id": 53252, "ts": "2026-08-23T18:09:48Z", "hours": 1.3772, "text": "I added a duration counter. It’s in seconds. No I’m not formatting it."}, {"post_id": 51227, "ts": "2026-08-20T19:17:11Z", "hours": 1.0561, "text": "Ran cargo fmt and spent an hour making sure that the playback is gapless and that my unsafe code wasn’t corrupting the memory. Also added a debug launch.json for vscode / vscodium users trying to debug it."}, {"post_id": 50713, "ts": "2026-08-20T01:29:33Z", "hours": 2.0586, "text": "Added settings page and very wisely used unsafe code to squish the sample playing loop, next up we have to address sample parsing since that can take a bit in prod. I will figure it out soon."}, {"post_id": 49982, "ts": "2026-08-19T00:27:51Z", "hours": 1.6133, "text": "Removed the about page that the ratings made apparent that no one read and started to add a settings page. I mean it has nothing at all."}, {"post_id": 48385, "ts": "2026-08-16T18:23:28Z", "hours": 1.2406, "text": "Added a lot to the README.md because it needs better documentation of features, also added file filtering."}, {"post_id": 47834, "ts": "2026-08-16T01:38:16Z", "hours": 0.7469, "text": "Made the controls better and remove a dependency. I also did some other stuff I am too tired to get into."}, {"post_id": 46089, "ts": "2026-08-13T01:40:56Z", "hours": 1.8419, "text": "The configuration update, make your own blindingly bright and eye-watering theme for GLAP today! (I did not put any restrictions on the theme, kinda almost but still might not work in terminal.app)"}, {"post_id": 45507, "ts": "2026-08-12T01:29:22Z", "hours": 2.1228, "text": "commiting now because its time for bed now. I am working on configuration. you know, custom themes, hiding the control bar, and the like. [EDIT]: IT DOESNT ACTUALLY PARSE THEM YET AND ITS BROKEN ANYWAY THIS COMMIT DOES NOT WORK"}, {"post_id": 44128, "ts": "2026-08-09T18:09:35Z", "hours": 2.0411, "text": "Fixes. I ran cargo clippy, added some v2 ideas, and generally cleaned up and optimized the code. Bumped version to v1.1.0 because the cargo overlords demand it, and also changed the controls thingy."}, {"post_id": 39016, "ts": "2026-08-01T17:53:06Z", "hours": 1.4003, "text": "I basically added rewinding and fast-forwarding. I also made the button unfocus with the window. I will ship soon™️"}, {"post_id": 38312, "ts": "2026-07-31T17:07:26Z", "hours": 0.5789, "text": "Probably the last devlog before Ship 1; I removed volume from the player because it just ate up memory and cpu cycles, and ran cargo fmt and cargo clippy for good measure. It’s pretty much done now."}, {"post_id": 37747, "ts": "2026-07-30T17:37:15Z", "hours": 1.4067, "text": "I’m almost done. I programmed in controls and repeating a folder of music (so basically playlists). It just repeats it in the displayed order so keep that in mind."}, {"post_id": 37205, "ts": "2026-07-29T19:03:10Z", "hours": 2.23, "text": "I am working on controls for the UI and them functioning. Making the elements focus right will be a pain. Well at least I’m in the home stretch. Unless of course I choose to split the backend of a crate… Meh I probably won’t do it."}, {"post_id": 36563, "ts": "2026-07-28T19:20:57Z", "hours": 2.0053, "text": "UI!!!!! I can use this kind of it still needs to be able to pause but it can resonably be considered an audio player now! This is so tiring but at least I can say that I’ve made something now."}, {"post_id": 35967, "ts": "2026-07-27T19:11:42Z", "hours": 1.9819, "text": "File explorer, playing thing from music folder, another archetecture redo, and a whole lot more."}, {"post_id": 35401, "ts": "2026-07-26T19:39:47Z", "hours": 0.6528, "text": "Async is actually async now."}, {"post_id": 35325, "ts": "2026-07-26T17:21:21Z", "hours": 1.0361, "text": "It kind of works… you need a file named sans.ogg in you music folder but nontheless it works. I still need a proper ui tho lol."}, {"post_id": 34766, "ts": "2026-07-25T19:07:01Z", "hours": 0.7131, "text": "The UI kind of works now, working on writing the about page. I still need to write the player code and page and what not, I will delegate this to a helper thread."}, {"post_id": 34732, "ts": "2026-07-25T18:04:40Z", "hours": 2.2267, "text": "Devlogging now because an electrical storm is nearby and I need to turn off my pc; basically just started to work on the ui. This one is not going to work so don’t build ."}, {"post_id": 34367, "ts": "2026-07-25T00:43:15Z", "hours": 0.8956, "text": "It plays now. I figure out gow to use the lock helper so I don’t have to screw around with mutexes and ownership and the like and still pause. Yay."}, {"post_id": 34199, "ts": "2026-07-24T18:34:35Z", "hours": 1.8939, "text": "I seperated some stuff into other files and started on the ui stuff with some basic boilerplate. It now doesn’t work again because I need to figure out how to use mutexes."}, {"post_id": 33079, "ts": "2026-07-22T17:40:50Z", "hours": 0.5153, "text": "Some smol optimizations"}, {"post_id": 33037, "ts": "2026-07-22T16:25:05Z", "hours": 0.5217, "text": "Mess around with feature flags and add some stuff to the README."}, {"post_id": 32442, "ts": "2026-07-21T17:12:04Z", "hours": 0.7594, "text": "It functions now. Yaey. Symphonia is complicated. I can now play songs with this. Next up: I struggle with some sort of UI thing to make a UI for it."}, {"post_id": 31883, "ts": "2026-07-20T17:09:26Z", "hours": 1.7542, "text": "Switched to Symphonia because FLAC audio is broken in Creak. At the moment the new implementation doesn’t function…"}, {"post_id": 31440, "ts": "2026-07-19T20:12:31Z", "hours": 0.5278, "text": "Made it play for the length of the song, added some logging, and a page enum."}, {"post_id": 30979, "ts": "2026-07-19T00:13:56Z", "hours": 0.4964, "text": "Rewrite the callback and run cargo fmt."}, {"post_id": 30872, "ts": "2026-07-18T20:31:03Z", "hours": 0.7356, "text": "It almost works, then I will work on a ui-ish thing."}, {"post_id": 30254, "ts": "2026-07-17T17:58:58Z", "hours": 1.135, "text": "Basically started to rewrite the entire project. TL;DR the Midi spec is a horribly built spec by modern standards, so I had the bright idea of make smth new. (I HAD SPECIFIC PERMISSION FROM RUPNIL TO DO THIS PLEASE DONT SLIME ME HERES A LINK TO THE THREAD FOR PROOF: https://hackclub.slack.com/archives/C0APH2MMHH7/p1784221925675859 )"}, {"post_id": 27754, "ts": "2026-07-13T16:16:20Z", "hours": 0.4494, "text": "We playin spot the difference with indices now."}, {"post_id": 26674, "ts": "2026-07-11T16:41:42Z", "hours": 0.7131, "text": "I re-implemented VLQ’s as a struct because midi is meen"}, {"post_id": 24225, "ts": "2026-07-07T17:25:21Z", "hours": 0.7889, "text": "I added some more data types, still cant parse yet tho"}, {"post_id": 21599, "ts": "2026-07-03T17:12:03Z", "hours": 0.4419, "text": "Apparently this is about to get more compicated…"}, {"post_id": 20957, "ts": "2026-07-02T18:08:22Z", "hours": 1.4392, "text": "Added some debug logging to assist with debugging!"}, {"post_id": 18492, "ts": "2026-06-29T17:34:54Z", "hours": 0.9272, "text": "Made some stuff make more sense to the programmer."}, {"post_id": 17757, "ts": "2026-06-28T17:54:57Z", "hours": 0.8472, "text": "I corrected indexing."}, {"post_id": 17056, "ts": "2026-06-27T18:10:41Z", "hours": 1.2067, "text": "More parsing. None of it actually works for now."}, {"post_id": 16388, "ts": "2026-06-26T17:47:00Z", "hours": 1.0394, "text": "I am parsing VLQ’s now!"}, {"post_id": 14500, "ts": "2026-06-23T17:20:18Z", "hours": 0.9022, "text": "I added some parsing for validity testing. The dumb part is that I still can’t parse messages fully because the MIDI standard can’t just use u32’s noooo they have to be soooooo fancy and use variable length quantities that are a headache to parse because they decided to do junk with raw bits for no reason other than to give midi player dev’s headaches and save a whopping 200 bytes in the file I’m working with (the song is straight fire tho). Oh yea I also added an ImHex project file bcs I’m not working with the MIDI docs because those get way to technical."}, {"post_id": 12669, "ts": "2026-06-20T18:12:02Z", "hours": 0.5386, "text": "I rewrote parsing to use structs because structs are cool."}, {"post_id": 10810, "ts": "2026-06-17T18:48:14Z", "hours": 0.5128, "text": "Added some rudimentary parsing. None of it does anything rn but it will at some point."}, {"post_id": 9390, "ts": "2026-06-15T18:51:51Z", "hours": 0.6078, "text": "Initalized project. TODO: Everything."}]...
|
Title: GLAP by @GameLord2011 | Stardance
Devlogs: Title: GLAP by @GameLord2011 | Stardance
Devlogs:
Initalized project. TODO: Everything.
Added some rudimentary parsing. None of it does anything rn but it will at some point.
I rewrote parsing to use structs because structs are cool.
I added some parsing for validity testing. The dumb part is that I still can’t parse messages fully because the MIDI standard can’t just use u32’s noooo they have to be soooooo fancy and use variable length quantities that are a headache to parse because they decided to do junk with raw bits for no reason other than to give midi player dev’s headaches and save a whopping 200 bytes in the file I’m working with (the song is straight fire tho). Oh yea I also added an ImHex project file bcs I’m not working with the MIDI docs because those get way to technical.
I am parsing VLQ’s now!
More parsing. None of it actually works for now.
I corrected indexing.
Made some stuff make more sense to the programmer.
Added some debug logging to assist with debugging!
Apparently this is about to get more compicated…
I added some more data types, still cant parse yet tho
I re-implemented VLQ’s as a struct because midi is meen
We playin spot the difference with indices now.
Basically started to rewrite the entire project. TL;DR the Midi spec is a horribly built spec by modern standards, so I had the bright idea of make smth new. (I HAD SPECIFIC PERMISSION FROM RUPNIL TO DO THIS PLEASE DONT SLIME ME HERES A LINK TO THE THREAD FOR PROOF: https://hackclub.slack.com/archives/C0APH2MMHH7/p1784221925675859 )
It almost works, then I will work on a ui-ish thing.
Rewrite the callback and run cargo fmt.
Made it play for the length of the song, added some logging, and a page enum.
Switched to Symphonia because FLAC audio is broken in Creak. At the moment the new implementation doesn’t function…
It functions now. Yaey. Symphonia is complicated. I can now play songs with this. Next up: I struggle with some sort of UI thing to make a UI for it.
Mess around with feature flags and add some stuff to the README.
Some smol optimizations
I seperated some stuff into other files and started on the ui stuff with some basic boilerplate. It now doesn’t work again because I need to figure out how to use mutexes.
It plays now. I figure out gow to use the lock helper so I don’t have to screw around with mutexes and ownership and the like and still pause. Yay.
Devlogging now because an electrical storm is nearby and I need to turn off my pc; basically just started to work on the ui. This one is not going to work so don’t build .
The UI kind of works now, working on writing the about page. I still need to write the player code and page and what not, I will delegate this to a helper thread.
It kind of works… you need a file named sans.ogg in you music folder but nontheless it works. I still need a proper ui tho lol.
Async is actually async now.
File explorer, playing thing from music folder, another archetecture redo, and a whole lot more.
UI!!!!! I can use this kind of it still needs to be able to pause but it can resonably be considered an audio player now! This is so tiring but at least I can say that I’ve made something now.
I am working on controls for the UI and them functioning. Making the elements focus right will be a pain. Well at least I’m in the home stretch. Unless of course I choose to split the backend of a crate… Meh I probably won’t do it.
I’m almost done. I programmed in controls and repeating a folder of music (so basically playlists). It just repeats it in the displayed order so keep that in mind.
Probably the last devlog before Ship 1; I removed volume from the player because it just ate up memory and cpu cycles, and ran cargo fmt and cargo clippy for good measure. It’s pretty much done now.
I basically added rewinding and fast-forwarding. I also made the button unfocus with the window. I will ship soon™️
Fixes. I ran cargo clippy, added some v2 ideas, and generally cleaned up and optimized the code. Bumped version to v1.1.0 because the cargo overlords demand it, and also changed the controls thingy.
commiting now because its time for bed now. I am working on configuration. you know, custom themes, hiding the control bar, and the like. [EDIT]: IT DOESNT ACTUALLY PARSE THEM YET AND ITS BROKEN ANYWAY THIS COMMIT DOES NOT WORK
The configuration update, make your own blindingly bright and eye-watering theme for GLAP today! (I did not put any restrictions on the theme, kinda almost but still might not work in terminal.app)
Made the controls better and remove a dependency. I also did some other stuff I am too tired to get into.
Added a lot to the README.md because it needs better documentation of features, also added file filtering.
Removed the about page that the ratings made apparent that no one read and started to add a settings page. I mean it has nothing at all.
Added settings page and very wisely used unsafe code to squish the sample playing loop, next up we have to address sample parsing since that can take a bit in prod. I will figure it out soon.
Ran cargo fmt and spent an hour making sure that the playback is gapless and that my unsafe code wasn’t corrupting the memory. Also added a debug launch.json for vscode / vscodium users trying to debug it.
I added a duration counter. It’s in seconds. No I’m not formatting it.
I did some general stability improvments and added error handling for the config (thanks @tkrl for bringing that to light).
Bump version, and do a boatload of under-the-hood microoptimizations and horribly unreadable code paired with next-to-no docs.
Added some doc comments because I plan to at some point have the audio-handling junk in a seperate crate so you can staple a frontend onto it. Okie now I can do v2.0
22 mins of trying and failing to convert it to sdl3. sdl2 forever
I added an audio graph and did some very many refactors.
Ships:
I basically made a TUI music player app in Rust, in the process learning how structs, ownership, threads, callbacks, and a bunch of other Rust things work. The hardest part was setting up the state handling. I am really proud of how this ended up.
I added configuration. I learned how serialization and deserialization work. I also learned how to document things. Thanks for everyone that helped with my project. Here’s an example theme to get you started with theming ([PHOTOSENSITIVE EPILEPISY WARNING]; also it doesn’t work on terminal.app because Apple is mean): [ theme ] background = "#b8d60e" foreground = "#ff00ff" controls = "#5f4808" playbar = "#00fff2"
I added a visualizer, learned a timing method, and squashed various bugs....
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de by @cat | Stardance
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Title: Web-OS by @XD | Stardance
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My awesome macropad! by @timotheyknezi | Stardance
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Title: My awesome macropad! by @timotheyknezi | St Title: My awesome macropad! by @timotheyknezi | Stardance...
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My awesome macropad! by @vivek_makkapati | Stardan My awesome macropad! by @vivek_makkapati | Stardance...
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Title: My awesome macropad! by @vivek_makkapati | Title: My awesome macropad! by @vivek_makkapati | Stardance...
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RootWeave by @maxoliver | Stardance
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[{"ship_num": 1, "ts": "2026-0 [{"ship_num": 1, "ts": "2026-06-19T16:43:21Z", "hours": 4.0, "multiplier": null, "payout": 0, "blessing": "neutral", "text": "I created a plugin for the popular note taking software obsidian.md. It creates native .md files inside a special folder, and while they are viewable without the plugin, the plugin allows you to easily translate, build words, import from other platforms, and ensure your conlang is cohesive. You can view a graph, hear your words pronunciation, or set it yourself, and more.", "repo": "https://github.com/molive6316github/rootweave", "demo": "https://community.obsidian.md/plugins/rootweave"}]...
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[{"post_id": 85232, "ts": "202 [{"post_id": 85232, "ts": "2026-10-31T00:17:19Z", "hours": 1.6931, "text": "I updated my readme, along with some other text, and i had a bunch of other little changes!"}, {"post_id": 11937, "ts": "2026-06-19T14:00:49Z", "hours": 0.4592, "text": "I enhanced translate by adding easy add, suggestions, and a few more qol"}, {"post_id": 11883, "ts": "2026-06-19T11:23:14Z", "hours": 1.4356, "text": "Built a phonology engine using a neural network, though i might have to use it for something else since its already there"}, {"post_id": 10561, "ts": "2026-06-17T11:07:09Z", "hours": 0.5581, "text": "I added a graph view(pictured) and a few QoL changes, along with rewriting some code. I am next going to work on a phonology engine which… uhhh… Itll definitely be interesting."}, {"post_id": 10246, "ts": "2026-06-16T21:33:50Z", "hours": 0.5661, "text": "I rewrote some code, patched some bugs, and added a importer."}, {"post_id": 10022, "ts": "2026-06-16T16:07:05Z", "hours": 0.7236, "text": "I have published the beta ver of the app to the obsidian community plugin list, which allows for easier installs and more discoverability. I still plan on upgrading the app, and adding new features."}, {"post_id": 9491, "ts": "2026-06-15T20:50:42Z", "hours": 0.3606, "text": "I have created a base outline, and it functions, however most code so far is ai outline, so i need to redo most of it."}]...
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Title: RootWeave by @maxoliver | Stardance
Devlog Title: RootWeave by @maxoliver | Stardance
Devlogs:
I have created a base outline, and it functions, however most code so far is ai outline, so i need to redo most of it.
I have published the beta ver of the app to the obsidian community plugin list, which allows for easier installs and more discoverability. I still plan on upgrading the app, and adding new features.
I rewrote some code, patched some bugs, and added a importer.
I added a graph view(pictured) and a few QoL changes, along with rewriting some code. I am next going to work on a phonology engine which… uhhh… Itll definitely be interesting.
Built a phonology engine using a neural network, though i might have to use it for something else since its already there
I enhanced translate by adding easy add, suggestions, and a few more qol
I updated my readme, along with some other text, and i had a bunch of other little changes!
Ships:
I created a plugin for the popular note taking software obsidian.md. It creates native .md files inside a special folder, and while they are viewable without the plugin, the plugin allows you to easily translate, build words, import from other platforms, and ensure your conlang is cohesive. You can view a graph, hear your words pronunciation, or set it yourself, and more....
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1793926347.5696645
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